With the continuous advancement and development in the semiconductor manufacture, the MOSFET devices are widely used in various integration circuits. The typical MOSFET device comprises of the gate structure formed on the substrate and the source and drain structures manufactured by forming the doping areas adjacent to the gate structure with the opposite dopant relative to the substrate. However, the performance of the manufactured device can not be promoted due to the sizes of the MOSFET devices are decreasing with the increasing package integration.
In general, the MOSFET device usually comprises a metal layer, a silicon oxide layer and a semiconductor substrate, wherein the metal layer is used to serve as the gate structure. Though, the polysilicon material is always used to substitute for the metal layer cause the adhesion of the polysilicon layer is better than the metal layer for the silicon oxide layer. It is not suitable to use only the polysilicon layer for serving as the gate structure due to the lower electrical conductivity of the polysilicon material into which even the dopant are implanted. Actually, in the present process, a metal silicide layer is formed on the polysilicon layer to promote the conductivity of the whole gate structure.
The typical manufacturing process and structure of the MOSFET are as illustrated in FIG. 1. At first a gate structure 20 is defined on a semiconductor substrate 10, wherein the gate structure 20 is a multi-layers structure which comprises the gate oxide layer 20a formed on the substrate 10, the polysilicon layer 20b formed on the gate oxide layer 20a, the metal silicide layer 20c formed on the polysilicon layer 20b, and the ARC (anti-reflected) layer 20d formed on the metal silicide layer 20c. Besides, the sidewall spacers 22 are formed on the sidewalls of the gate structure 20. Then, the source and drain areas are defined by forming the doping areas 24 in the semiconductor substrate 10 adjacent to the gate structure 20.
In general, after the MOSFET device structure is formed, the non-doped silicate glass (NSG) 26 is coated onto the substrate 10 to cover the MOSFET device. The NSG layer 26 is used to prevent the electrical conductivity of the MOSFET device from varying due to the dopant of the BPSG (Borophosphosilicate Glass) layer formed in the next step can diffuse into the MOSFET device. Then, the BPSG layer 28 is formed on the substrate 10 to cover the NSG layer 26 for serving as the inter-metal layer (IMD). After forming the BPSG layer 28, a thermal flow procedure is performed about 30 to 120 minutes at a temperature of about 850 to 950.degree. C. to promote the planarization of the BPSG layer 28.
However, after performing the thermal flow procedure, peeling and delamination usually occur between the interface of the NSG layer 26 and the oxynitride layer 20d because the adhesions among the NSG layer 26, the oxynitride layer 20d and the metal silicide layer 20c are worse. Thus, the performance and yields of the manufactured devices are both decreased.